Electronic products rely on integrated circuits (ICs) which can contain many millions or even billons of transistors and other electronic structures such as resistors, capacitors, diodes, and interconnecting conductors. The design process for modern ICs involves many different steps to help manage the complexity and produce an IC that functions as intended. One of the design steps involves implementing a physical verification process, which is typically highly automated. The physical verification process for an integrated circuit (IC) is a design step taken by semiconductor manufacturers before commencing the fabrication of an IC. Physical verification involves implementing sets of checks on a design to ensure that physical structures on a chip behave in a predictable and acceptable manner in accordance with a design's intent. To perform physical verification, semiconductor foundries first define a set of so-called design rules for manufacturing (DRM) for IC designers to follow. The DRM outline a set of geometric relationships between manufacturing layers and features in a design layout, layers which in turn are used to create an IC. The defining of DRM allows a set of known good parameters for a design to be compared with the actual physical design layout, which can include hundreds of layers used during the fabrication process to create transistors and electrical interconnect in the IC. If the design violates the DRM in a certain location, the location represents a potential issue or failing requiring attention before manufacturing can commence. The semiconductor process has grown in complexity such that a physical design layout must adhere to thousands of design rules before a design can be successfully fabricated and produce a high yield during the fabrication process.
Use of a design rule checking (DRC) physical verification tool is an industry standard process for implementing the semiconductor's DRM. While the DRM itself can define many different parameters, such as width, spacing, angle, enclosure, density and electrical connectivity rules for design layers, the parameters are translated into a DRC runset—a set of DRC operations that verify the required DRM rules—before actual verification can commence. A DRC tool provides a large set of DRC commands from which a designer draws in order to build a specialized sequence of commands to verify and satisfy each DRM rule for a design. This is not a simple task. DRM rules commonly result in a DRC runset with 20,000 or more DRC commands for technology nodes smaller than 28 nanometers (nm). Modern DRC physical verification tools have a large suite of geometric and electrical commands to effectively implement the complex DRM rules. However, many of the geometric and electrical DRC commands result in the implementation of unique algorithms that are not shared between individual commands, thus resulting in a very complex DRC tool requiring the implementation of numerous algorithms to complete the DRM checking.
Large ICs are typically built using a hierarchical method that begins with the creation of small child cells which are combined into larger parent cells, which then are successively used to build larger and larger cells to create an IC hierarchical design. Physical verification tools take advantage of the hierarchy in a design to efficiently process today's extremely large designs. Various forms of data-integrating processes may offer an alternative to the numerous algorithms required hierarchical processing, but these processes often result in data flattening, and thus cause very large increases in processing time, an infeasible tradeoff for modern design verification.